Comparison ledger
SPTS CET25 and SPTS Rapier, side by side. Every value shown is drawn from its cited encyclopedia entry.
| Attribute | CET25SPTS | RapierSPTS |
|---|---|---|
| OEM | SPTS | SPTS |
| Category | Etch | Etch |
| Wafer size | 25-wafer batch | Silicon and Silicon on Insulator (SOI) wafers |
| Process node | — | — |
| Introduced | — | — |
| Production run | — | — |
| Lifecycle | — | — |
| Lifecycle milestones | — | — |
| Control system | — | — |
| Generation | — | — |
| Family | SPTS CET25 | SPTS Rapier |
| Specifications | ||
| Process type | HF vapor release etch for MEMS[1] | Optimized Deep Reactive Ion Etching (DRIE) system[2] |
| Batch size | 25-wafer batch[1] | — |
| Target application | Medium to high volume production applications[1] | — |
| Key benefits | High throughput; process chamber, gas and liquid panel, and pressure control components within a small footprint; extensive process control and monitoring functions[1] | — |
| Configuration support | Various SPTS cluster configurations with the ability to support multiple process modules[1] | — |
| Wafer materials | — | Silicon (Si) and Silicon on Insulator (SOI) wafers[2] |
| Loader capacity | — | Single vacuum cassette loader, 25 wafers capacity[2] |
| Transport robot | — | Brooks Magnatran 7 transport robot[2] |
| Plasma source | — | Dual high density Inductive Coupled Plasma (ICP) source[2] |
| Clamping | — | Electrostatic Clamping Chuck (ESC)[2] |
| Wafer biasing | — | Radio and low frequencies wafer biasing, with pulsing possibility[2] |
| Mass flow controllers | — | High speed digital mass flow controllers[2] |
| Endpoint systems | — | Amplified optical emission spectroscopy endpoint system; white light interferometry endpoint system[2] |
| Software | — | Powerful software with ramping curves of process parameters with time[2] |
| Module configuration | — | Unique, patented dual plasma source with multiple operating modes[2] |
| RF sources | — | Two RF independent sources, up to 3 kW each[2] |
| Gas showers | — | Two independent gas showers (center and edge zones)[2] |
| Temperature control | — | Ranges from -10°C to 30°C[2] |
| RF wafer biasing | — | Up to 2 kW with pulsing possibility and duty cycle control[2] |
| Low frequency wafer biasing | — | Up to 1.2 kW with pulsing possibility and duty cycle control[2] |
| Wafer-less conditioning | — | Chamber plasma conditioning or self-cleaning can run wafer-less if needed[2] |
| Available process gases | — | 2x SF6 720 sccm; 2x C4F8 500 sccm; O2 300 sccm and 1000 sccm; Ar 500 sccm; N2 100 sccm[2] |
| Standard process: DRIE Trench | — | Trench 2 µm: 300 nm/loop; trench >200 µm: 800 nm/loop[2] |
| Standard process: HAR Hole | — | 10 µm: 200 nm/loop; trench 2 µm: 165 nm/loop[2] |
| Standard process: DRIE-Nano Trench | — | 350 nm: 150 nm/loop; scallops <50 nm; depth limited to tens of µm[2] |
| Standard process: Opto | — | From 130 nm/min to 370 nm/min; continuous etch process; for shallow and accurate etch; less than 2 µm deep[2] |
| Standard process: Si_Release | — | ~3 µm/min lateral and ~6 µm/min vertical; continuous etch process; isotropic etching of silicon[2] |
| Standard process: Oxide_RIE | — | SiO2: 235 nm/min; Si3N4: 110 nm/min; PR etch rate 170 nm/min; thin layers only (<1 µm); O2 cleaning compulsory[2] |
| Standard process: BARC DUV42P | — | 78 nm/min; Si: 50 nm/min; anti-reflective coating opening after DUV litho[2] |
| Standard process: Wafer thinning | — | 4.4 µm/min; uniformity +/- 3.5%[2] |
| Standard process: Dicing | — | Design dicing streets only (150 µm): 3.4 µm/loop; not for structures <10 µm[2] |
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