Waferpedia

SPTS

Rapier

Rapier — epfl.ch
Fig. 01Rapierepfl.ch[1]
  • Plate 01yippeee rapier :3 #hema #historicalfencing #sca #sword #rapier

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  • Plate 02🤺 rapier fencing lesson : thrust parry cut ⚔️ #defense #sword #milwaukee @cfsmke

    Discovered Fencers MKEWatch on YouTube
  • Plate 03HEMA RAPIER - Can Rapiers cut?? Sources say sure

    Kyle ThrushWatch on YouTube
  • Plate 04⚔️ Counter-Parry & Riposte by Disengagement & Yielding Glide #rapier #historicalfencing #swordplay

    Boston Academie d'ArmesWatch on YouTube
  • Plate 05SPT in Rapier & Dagger 2021 - John Leggett

    John LeggettWatch on YouTube
  • Plate 06Italian Rapier vs Sports Epee | HEMA vs Sport fencing | Weapon Confrontations - part 1

    Akademia SzermierzyWatch on YouTube
  • Plate 07HEMA Rapier- Squinter from Longpoint

    Kyle ThrushWatch on YouTube
  • Plate 08⚔️ Yielding Parry & Circular Cut #stramazzone #historicalfencing #fencingtactics #pennsic #rapier

    Justin Aucoin - Historical SwordplayWatch on YouTube
  • Plate 09Sunbeam Rapier Series V (Series 5) - the rare 1960s British sporting saloon!

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  • Plate 10JT Atwood Rapier and Dagger SPT 2024

    JT AtwoodWatch on YouTube

Wafer size

Silicon and Silicon on Insulator (SOI) wafers

Gas delivery

High speed digital mass flow controllers[1]

What is it?

The SPTS Rapier etcher is described as an optimized DRIE system for silicon (Si) and silicon-on-insulator (SOI) wafers. The source states that it includes a single vacuum cassette loader with 25-wafers capacity, a Brooks Magnatran 7 transport robot, a dual high density inductive coupled plasma source, electrostatic clamping, wafer biasing with pulsing, mass flow controllers, end-point systems, and software with ramping curves for process parameters.

What can it run?

Process applications and technology nodes documented for this tool.

  • Deep reactive ion etching of silicon and silicon-on-insulator wafers
  • Trench etching
  • Hole etching
  • Nano-pulsed etching
  • Optical etching
  • Silicon release
  • Oxide RIE
  • BARC opening
  • Wafer thinning
  • Dicing

Why won't it start?

Documented failure modes, common issues, and field considerations.

  • The source notes that etch rates are design dependent and reduce with time and increasing aspect ratio (ARDE).
  • For the HAR hole process, the source states the last 300 nm of mask is not viable because of faceting.
  • For the Dicing process, the source states it is not for structures smaller than 10 µm due to too large CD loss.

What do the numbers mean?

Power & electrical3

RF sources
Two RF independent sources, up to 3 kW each[1]
Accurate?
RF wafer biasing
Up to 2 kW with pulsing possibility and duty cycle control[1]
Accurate?
Low frequency wafer biasing
Up to 1.2 kW with pulsing possibility and duty cycle control[1]
Accurate?

Vacuum & pumping1

Loader capacity
Single vacuum cassette loader, 25 wafers capacity[1]
Accurate?

Wafer handling6

Wafer materials
Silicon (Si) and Silicon on Insulator (SOI) wafers[1]
Accurate?
Transport robot
Brooks Magnatran 7 transport robot[1]
Accurate?
Clamping
Electrostatic Clamping Chuck (ESC)[1]
Accurate?
Wafer biasing
Radio and low frequencies wafer biasing, with pulsing possibility[1]
Accurate?
Wafer-less conditioning
Chamber plasma conditioning or self-cleaning can run wafer-less if needed[1]
Accurate?
Standard process: Wafer thinning
4.4 µm/min; uniformity +/- 3.5%[1]
Accurate?

Gas & chemistry3

Mass flow controllers
High speed digital mass flow controllers[1]
Accurate?
Gas showers
Two independent gas showers (center and edge zones)[1]
Accurate?
Available process gases
2x SF6 720 sccm; 2x C4F8 500 sccm; O2 300 sccm and 1000 sccm; Ar 500 sccm; N2 100 sccm[1]
Accurate?

Optics & imaging7

Endpoint systems
Amplified optical emission spectroscopy endpoint system; white light interferometry endpoint system[1]
Accurate?
Standard process: DRIE Trench
Trench 2 µm: 300 nm/loop; trench >200 µm: 800 nm/loop[1]
Accurate?
Standard process: HAR Hole
10 µm: 200 nm/loop; trench 2 µm: 165 nm/loop[1]
Accurate?
Standard process: DRIE-Nano Trench
350 nm: 150 nm/loop; scallops <50 nm; depth limited to tens of µm[1]
Accurate?
Standard process: Opto
From 130 nm/min to 370 nm/min; continuous etch process; for shallow and accurate etch; less than 2 µm deep[1]
Accurate?
Standard process: Oxide_RIE
SiO2: 235 nm/min; Si3N4: 110 nm/min; PR etch rate 170 nm/min; thin layers only (<1 µm); O2 cleaning compulsory[1]
Accurate?
Standard process: BARC DUV42P
78 nm/min; Si: 50 nm/min; anti-reflective coating opening after DUV litho[1]
Accurate?

Control & software2

Software
Powerful software with ramping curves of process parameters with time[1]
Accurate?
Temperature control
Ranges from -10°C to 30°C[1]
Accurate?

Configuration & options5

Process type
Optimized Deep Reactive Ion Etching (DRIE) system[1]
Accurate?
Plasma source
Dual high density Inductive Coupled Plasma (ICP) source[1]
Accurate?
Module configuration
Unique, patented dual plasma source with multiple operating modes[1]
Accurate?
Standard process: Si_Release
~3 µm/min lateral and ~6 µm/min vertical; continuous etch process; isotropic etching of silicon[1]
Accurate?
Standard process: Dicing
Design dicing streets only (150 µm): 3.4 µm/loop; not for structures <10 µm[1]
Accurate?
Interested in this tool?
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What replaced it?

What does it need to run?

Site utility requirements, footprint, and infrastructure needed to install and operate this tool. Sourced from public records.

  • Loader capacitySingle vacuum cassette loader, 25 wafers capacity[1]
  • Mass flow controllersHigh speed digital mass flow controllers[1]
  • RF sourcesTwo RF independent sources, up to 3 kW each[1]
  • Gas showersTwo independent gas showers (center and edge zones)[1]
  • RF wafer biasingUp to 2 kW with pulsing possibility and duty cycle control[1]
  • Low frequency wafer biasingUp to 1.2 kW with pulsing possibility and duty cycle control[1]
  • Available process gases2x SF6 720 sccm; 2x C4F8 500 sccm; O2 300 sccm and 1000 sccm; Ar 500 sccm; N2 100 sccm[1]

Where are the manuals?

Generated from public-source data on file. Enter your email to access — nothing is published; details are routed privately.

Not publicly documented

Field notes

No research found yet — worked with this tool? Share what you know.

Not publicly documented

The following facts about the Rapier are absent from this record as of this revision. First-hand knowledge or a citation closes a gap; every submission is reviewed before publication.

  • No publicly documented production dates or lifecycle milestones (introduction, end of production, EOL) for the Rapier are on record.

    Answerable by: OEM historical records or a trade-press announcement

  • No publicly documented variants, configuration options, or revision breakpoints of the Rapier are on record.

    Answerable by: an OEM product catalog or an engineer who ordered or specified the tool

  • The control-system platform and OS era of the Rapier are not on record.

    Answerable by: an engineer who operated it or OEM installation records

  • The process node or technology generation of the Rapier is not on record.

    Answerable by: an OEM datasheet or a fab qualification report

  • No publicly documented compatible parts, consumables, or accessories for the Rapier are on record.

    Answerable by: an OEM parts catalog or a service engineer

Sources & citations

Sources (5)Every fact above is drawn from these public sources
  1. [1]epfl.chepfl.chepfl.ch
  2. [2]epfl.chepfl.ch
  3. [3]Dry Etchingtudelft.nltudelft.nl
  4. [4]Tool Details - Harvard CNScns1.rc.fas.harvard.educns1.rc.fas.harvard.edu
  5. [5]SPTS Si DRIE processesspts.com (Apr 25, 2018)web.archive.org
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Last updated Jul 29, 2026.

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