Waferpedia

Comparison ledger

Rapier versus XeF2

SPTS Rapier and SPTS XeF2, side by side. Every value shown is drawn from its cited encyclopedia entry.

Side-by-side comparison of selected equipment models
Attribute
RapierSPTS
XeF2SPTS
OEMSPTSSPTS
CategoryEtchEtch
Wafer sizeSilicon and Silicon on Insulator (SOI) wafersUp to 6-inch wafers
Process node
Introduced
Production run
Lifecycle
Lifecycle milestones2013 Acquisition of XACTIX, Inc. · 2013 XACTIX acquisition
Control system
Generation
FamilySPTS RapierSPTS XeF2
Specifications
Process typeOptimized Deep Reactive Ion Etching (DRIE) system[1]
Wafer materialsSilicon (Si) and Silicon on Insulator (SOI) wafers[1]
Loader capacitySingle vacuum cassette loader, 25 wafers capacity[1]
Transport robotBrooks Magnatran 7 transport robot[1]
Plasma sourceDual high density Inductive Coupled Plasma (ICP) source[1]
ClampingElectrostatic Clamping Chuck (ESC)[1]
Wafer biasingRadio and low frequencies wafer biasing, with pulsing possibility[1]
Mass flow controllersHigh speed digital mass flow controllers[1]
Endpoint systemsAmplified optical emission spectroscopy endpoint system; white light interferometry endpoint system[1]
SoftwarePowerful software with ramping curves of process parameters with time[1]
Module configurationUnique, patented dual plasma source with multiple operating modes[1]
RF sourcesTwo RF independent sources, up to 3 kW each[1]
Gas showersTwo independent gas showers (center and edge zones)[1]
Temperature controlRanges from -10°C to 30°C[1]
RF wafer biasingUp to 2 kW with pulsing possibility and duty cycle control[1]
Low frequency wafer biasingUp to 1.2 kW with pulsing possibility and duty cycle control[1]
Wafer-less conditioningChamber plasma conditioning or self-cleaning can run wafer-less if needed[1]
Available process gases2x SF6 720 sccm; 2x C4F8 500 sccm; O2 300 sccm and 1000 sccm; Ar 500 sccm; N2 100 sccm[1]
Standard process: DRIE TrenchTrench 2 µm: 300 nm/loop; trench >200 µm: 800 nm/loop[1]
Standard process: HAR Hole10 µm: 200 nm/loop; trench 2 µm: 165 nm/loop[1]
Standard process: DRIE-Nano Trench350 nm: 150 nm/loop; scallops <50 nm; depth limited to tens of µm[1]
Standard process: OptoFrom 130 nm/min to 370 nm/min; continuous etch process; for shallow and accurate etch; less than 2 µm deep[1]
Standard process: Si_Release~3 µm/min lateral and ~6 µm/min vertical; continuous etch process; isotropic etching of silicon[1]
Standard process: Oxide_RIESiO2: 235 nm/min; Si3N4: 110 nm/min; PR etch rate 170 nm/min; thin layers only (<1 µm); O2 cleaning compulsory[1]
Standard process: BARC DUV42P78 nm/min; Si: 50 nm/min; anti-reflective coating opening after DUV litho[1]
Standard process: Wafer thinning4.4 µm/min; uniformity +/- 3.5%[1]
Standard process: DicingDesign dicing streets only (150 µm): 3.4 µm/loop; not for structures <10 µm[1]
Etch typeIsotropic etch[2]
SelectivityOver 1000:1 between Si/photoresist, Si/SiO2, and Si/SiN[2]
Gas flow modesContinuous and pulsed gas flow[2]
Operating temperatureRoom temperature[2]
PlasmaNo plasma[2]
Substrate sizeUp to 6-inch wafers[2]
Isotropic etch materialsSi, Mo, Ge, W, C[2]

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Sources (2)Every fact above is drawn from these public sources
  1. [1]epfl.chepfl.ch
  2. [2]aggiefab.tamu.eduaggiefab.tamu.edu