Comparison ledger
SPTS APS, Tegal 110, side by side. Every value shown is drawn from the cited encyclopedia entries.
| Attribute | APSSPTS | 110Tegal |
|---|---|---|
| OEM | SPTS | Tegal |
| Category | Etch | Etch |
| Wafer size | — | — |
| Process node | — | — |
| Introduced | — | — |
| Production run | — | — |
| Lifecycle | — | — |
| Lifecycle milestones | — | — |
| Control system | — | — |
| Generation | — | — |
| Family | SPTS APS | Tegal 110 |
| Cited variants | — |
|
| Specifications | ||
| System type | ICP-based high density plasma source[2] | plasma etch system[3] |
| Optimization target | Dielectric etching[2] | — |
| Processing mode | Single wafer processing[2] | — |
| Clamping | Electrostatic clamping[2] | — |
| End-point detection | Optical Emission Spectroscopy (EOS) and laser reflectometry/interferometry[2] | — |
| Gases available | O2, Ar, CHF3, He, C4F8, SF6, H2[2] | — |
| Plasma source type | ICP (inductively coupled plasma) high density plasma source[2] | — |
| Available gases | O2 (0-100 sccm), Ar (0-100 sccm), CHF3 (0-100 sccm), He (0-500 sccm), C4F8 (0-100 sccm), SF6 (0-100 sccm & 0-500 sccm), H2 (0-50 sccm)[2] | — |
| Wafer clamping | Electrostatic clamping (no EBR required)[2] | — |
| Wafer voltage biasing | Independent from the ICP[2] | — |
| Process chamber | Single wafer processing with loadlock[2] | — |
| Process type | ICP-based high density plasma source[2] | — |
| Etch materials | Dielectrics: SiO2, SixNy, SiC, Al2O3, glass types[2] | — |
| Wafer bias | Wafer voltage biasing independent from the ICP[2] | — |
| Wafer handling | Loadlock/chamber transfers for single wafer processing[2] | — |
| Automation | Control software offering fully automated processes[2] | — |
| Process gases | O2 (0-100 sccm), He (0-500 sccm), SF6 (0-100 sccm), H2 (0-50 sccm), plus Ar, CHF3, C4F8[2] | — |
| Stated processes | BARC_Slow, Si3N4_Smooth, SiO2_PR_1:1, SiO2_PR_2:1, SiO2_PR_3:1, SiO2_PR_3:1_SOFT, SiO2_PR_5:1, SiO2_PR_soft, Pi_vertical, Pi_tapered, Fused_silica, Pyrex, LiNbO3_wafers, Chamber clean[2] | — |
| Chuck temperature | 10 °C for most processes, 20 °C for fused silica, 25 °C for Pyrex, -10 °C for LiNbO3[2] | — |
| Maximum etch time | 20 minutes for processes marked with *; longer etches are split into steps with an automatic O2 dry clean between each[2] | — |
| Wafer cooling check | Helium leak-up rate (LUR) must not exceed 200 mtorr/min[2] | — |
| Plasma source | ICP-based high density plasma source[2] | — |
| Wafer biasing | Independent from ICP[2] | — |
| Control software | Offers fully automated processes[2] | — |
| Endpoint detection | Optical Emission Spectroscopy (EOS) and laser reflectometry/interferometry[2] | — |
| Maximum leak-up rate for wafer cooling | 200 mtorr/min[2] | — |
| model | — | 110 SE[1] |
| application focus | — | process development applications[1] |
| process capability | — | deep silicon plasma etching[1] |
| capabilities | — | very high aspect ratio trench etch and profile control[1] |
| configuration | — | multiple configurations with minimum technical intervention[1] |
| Supported components | — | MEMS and 3D-IC components[1] |
| Control capability | — | very high aspect ratio trench etch and profile control[3] |
| Physical description | — | compact[1] |
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