SPTS
RIE-10
The SPTS RIE-10 is a deep silicon etching system with dual plasma sources and dual gas inlets. The SPTS RIE-10 achieves an etch rate of 6–10 µm/min and aspect ratio up to 50:1. The SPTS RIE-10 uses fixed RF matching technology for reduced step-process time and controllable side wall roughness below 6 nm.[1][2]
Wafer size
6-inch wafers
Power
up to 3,000 W[1]
Performance
6–10 µm/min[1]
Gas delivery
>50:1[1]
Optics
Claritas End Point Detector[1]
What it is
How it works
The SPTS RIE-10 uses dual plasma sources and dual gas inlets. The SPTS RIE-10 includes fixed RF matching technology. The SPTS RIE-10 has primary RF power up to 3,000 W, secondary RF power up to 3,000 W, and substrate power up to 300 W. The SPTS RIE-10 has chuck temperatures from -15°C to +40°C. The SPTS RIE-10 includes a Claritas End Point Detector. The SPTS RIE-10 is characterized with an etch rate of 6–10 µm/min, aspect ratio up to 50:1, selectivity greater than 50:1 to resist, selectivity greater than 100:1 to silicon oxide, and uniformity below 5% across 6-inch wafers. The SPTS RIE-10 uses fixed RF matching technology to reduce step-process time to 1 second and to provide controllable side wall roughness below 6 nm for nanoscale features.[1][3][2]
Where it fits in the process flow
The SPTS RIE-10 is suited to fabrication steps that require deep silicon removal, high aspect ratio features, and through-wafer etching. The SPTS RIE-10 supports deep etch from 5 µm through silicon wafer etch. The SPTS RIE-10 supports broad lateral feature sizes from nano-scale to millimeter-scale.[1][3][2]
What can it run?
Process applications and technology nodes documented for this tool.
- Si etch only
- High aspect ratio etch
- Deep etch
- Broad feature sizes from nano- to mm-scale in lateral dimension
- Micro pillars
- Nano pillars
- Micro trenches
- Nano trenches
- Via etch
- Through wafer via etch
- Wafer thinning
What do the numbers mean?
Power & electrical3
Wafer handling5
Gas & chemistry3
Optics & imaging5
Performance1
Configuration & options7
What does it need to run?
Site utility requirements, footprint, and infrastructure needed to install and operate this tool. Sourced from public records.
Where are the manuals?
Generated from public-source data on file. Enter your email to access — nothing is published; details are routed privately.
Not publicly documented
Field notes
No research found yet — worked with this tool? Share what you know.
Frequently asked questions
Not publicly documented
The following facts about the RIE-10 are absent from this record as of this revision. First-hand knowledge or a citation closes a gap; every submission is reviewed before publication.
No publicly documented production dates or lifecycle milestones (introduction, end of production, EOL) for the RIE-10 are on record.
Answerable by: OEM historical records or a trade-press announcement
No publicly documented variants, configuration options, or revision breakpoints of the RIE-10 are on record.
Answerable by: an OEM product catalog or an engineer who ordered or specified the tool
The control-system platform and OS era of the RIE-10 are not on record.
Answerable by: an engineer who operated it or OEM installation records
No publicly documented failure modes or field errata for the RIE-10 are on record.
Answerable by: a field service engineer, process engineer, or maintenance technician
The process node or technology generation of the RIE-10 is not on record.
Answerable by: an OEM datasheet or a fab qualification report
No research found yet — worked with this tool? Share what you know.
Sources & citations
Sources (4)Every fact above is drawn from these public sources
- [1]cns1.rc.fas.harvard.edu — cns1.rc.fas.harvard.educns1.rc.fas.harvard.edu
- [2]SPTS Technologies SPTS RIE-10 Omega LPX Rapier SPTS Rapier DRIE | SemiStar — semistarcorp.comsemistarcorp.com
- [3]waferpedia.com — waferpedia.comwaferpedia.com
- [4]SPTS RIE-10 family | Waferpedia — waferpedia.comwaferpedia.com
Last updated Oct 20, 2026.
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