Reference
Plain-language, cited definitions of the terminology used across the encyclopedia.
A film-growth technique that exposes the wafer to alternating, self-limiting precursor pulses, depositing the film one atomic layer at a time. Because each cycle saturates, ALD delivers angstrom-level thickness control and perfectly conformal coverage of high-aspect-ratio structures, at the cost of slow deposition rates.
Removal of remaining photoresist after etch or implant by oxidizing it in an oxygen plasma, converting the organic resist to volatile products. Ashing (resist stripping) systems are usually downstream-plasma tools designed to avoid ion damage to the device layers.
Computer-controlled systems that apply stimulus and measure response to verify a device works to specification, at wafer probe and again after packaging (final test). ATE ranges from parametric testers to massively parallel memory and SoC test cells docked to probers and handlers.
A controlled heat treatment used to repair crystal damage after ion implantation, electrically activate dopants, densify deposited films, form silicides, or relieve stress. Anneals range from long furnace cycles to rapid thermal, spike, flash, and laser anneals with progressively shorter thermal budgets.
The size of the smallest printed feature that must be controlled in a given process layer, such as a transistor gate width. Critical dimensions are measured after develop and after etch — typically with CD-SEM or scatterometry tools — to verify the lithography and etch steps stayed within specification.
A manufacturing environment in which airborne particle concentration is controlled to a specified class (e.g. ISO 5) by HEPA/ULPA-filtered laminar airflow, controlled temperature and humidity, and gowning protocols. Semiconductor fabs require cleanrooms because a single sub-micron particle can kill a die.
A film-growth process in which gaseous precursors react on or near the heated wafer surface to deposit a solid film, such as polysilicon, silicon dioxide, silicon nitride, or tungsten. Variants are distinguished by pressure and energy source — atmospheric (APCVD), low-pressure (LPCVD), and plasma-enhanced (PECVD).
A polishing process — also called chemical mechanical polishing or CMP — that flattens the wafer surface by pressing it against a rotating pad flooded with abrasive, chemically active slurry. CMP planarizes dielectric layers between metal levels and removes excess metal in damascene copper and tungsten-plug flows.
A highly anisotropic plasma etch used to create deep, near-vertical structures in silicon — trenches and holes with aspect ratios far beyond ordinary RIE. The dominant implementation, the Bosch process, alternates short etch and fluoropolymer passivation cycles. DRIE is a workhorse for MEMS and through-silicon vias.
A hot-wall tube furnace that processes batches of wafers at temperatures up to about 1200 °C for oxidation, dopant drive-in and diffusion, anneals, and LPCVD film growth. Vertical furnaces largely replaced horizontal tubes at 200 mm and beyond for better uniformity, cleanliness, and floor-space efficiency.
Attaching a singulated die to its package substrate or leadframe — with epoxy adhesive, solder, or eutectic bonding — as the first step of packaging. Die bonders pick known-good die from the diced wafer and place them with high positional accuracy before wire bonding or flip-chip interconnect.
Extreme-ultraviolet lithography, an exposure technology using 13.5 nm light produced by a laser-driven tin plasma. Because nearly all materials absorb EUV, the optical path uses reflective multilayer mirrors in vacuum rather than lenses. EUV enables single-exposure patterning of features that would otherwise need multiple deep-UV patterning passes.
Growth of a crystalline layer on a crystalline substrate such that the new layer continues the substrate's crystal lattice. Silicon epitaxy in CVD reactors provides the lightly doped device layer on heavily doped wafers; compound-semiconductor epitaxy (MOCVD, MBE) builds the layered structures behind LEDs, lasers, and RF devices.
An optical measurement that determines film thickness and refractive index from the change in polarization of light reflected off the wafer. Because it is non-contact and sensitive to sub-nanometer thickness changes, spectroscopic ellipsometry is the standard way thin transparent films are monitored in the fab.
Electrochemical deposition of metal from a solution onto a conductive seed layer on the wafer. Copper electroplating (electrochemical deposition, ECD) fills the damascene trenches and vias of modern interconnect stacks, and thick plated layers form bumps and pillars for advanced packaging.
The ratio of the etch rate of the target film to the etch rate of other exposed materials, such as the masking resist or the layer underneath. High selectivity lets an etch stop cleanly on an underlying film; low selectivity erodes the mask and attacks the substrate.
A packaging interconnect scheme in which solder bumps are formed on the die's pads, the die is flipped face-down, and the bumps are reflowed directly onto the substrate — replacing peripheral bond wires with an area array of short connections that support far higher I/O counts and better electrical performance.
Front Opening Unified Pod: the sealed plastic carrier that holds a lot of 300 mm wafers in a clean mini-environment as it moves between tools. Tools dock FOUPs on standardized load ports and open them through a front-opening interface, so wafers travel the fab without exposure to ambient air.
A sheet-resistance measurement using four in-line probe tips: current is forced through the outer pair while voltage is sensed across the inner pair, eliminating contact resistance from the reading. Four-point probes verify implant dose, anneal activation, and deposited metal film thickness.
Low-pressure chemical vapor deposition: thermal CVD carried out at reduced pressure, typically in a hot-wall tube furnace holding many wafers. Operating at low pressure makes film growth surface-reaction limited, giving LPCVD films — polysilicon, nitride, TEOS oxide — excellent uniformity and conformality across large batches.
The standardized station on the front of a production tool where a wafer carrier (FOUP or SMIF pod) is placed — by an operator or overhead transport system — docked, and opened so the tool's robot can access the wafers. Load-port dimensions and behavior are defined by SEMI standards so any carrier fits any tool.
Metalorganic chemical vapor deposition: epitaxial growth of compound-semiconductor layers (GaN, GaAs, InP and their alloys) from metalorganic and hydride precursors. MOCVD reactors are the primary production tools for LEDs, laser diodes, and GaN power and RF devices.
Particle removal that couples high-frequency (~1 MHz) acoustic energy into the cleaning liquid, creating controlled microcavitation and acoustic streaming that dislodge sub-micron particles without the surface damage lower-frequency ultrasonic agitation can cause on fine structures.
Epitaxial growth performed in ultra-high vacuum by directing thermal beams of the constituent elements at a heated substrate. MBE offers monolayer-level control and abrupt interfaces, making it the tool of choice for research heterostructures and certain production III-V devices.
A light-sensitive polymer coating applied to the wafer before exposure. In positive resists the exposed regions become soluble in developer; in negative resists the exposed regions cross-link and remain. The developed resist pattern acts as a temporary mask for etching or ion implantation and is stripped afterwards.
A family of vacuum coating processes — chiefly sputtering and evaporation — in which the film material is physically transported from a solid source to the wafer without a chemical reaction forming the film. PVD is used for metal interconnect layers, barrier and adhesion layers, and backside metallization.
A patterning process that uses light to transfer a geometric design from a photomask onto a light-sensitive photoresist coated on the wafer. Exposed (or unexposed) resist is then developed away, leaving a pattern that masks subsequent etch or implant steps. Photolithography defines the smallest features a fab can print and is typically the most expensive step sequence in wafer processing.
Plasma-enhanced chemical vapor deposition: a CVD variant in which an RF plasma supplies the energy that drives the deposition chemistry, allowing films such as silicon nitride and oxide to be deposited at much lower wafer temperatures than thermal CVD — essential once metal layers that cannot tolerate high temperatures are present.
Removal of material from the wafer surface by reactive species generated in a glow-discharge plasma. Feed gases such as fluorine- or chlorine-bearing compounds are dissociated in the plasma, react with the exposed film, and form volatile products that are pumped away. Plasma etching replaced most wet etching for pattern transfer because it can be made directional.
The consumable interface between a wafer prober and the test system: an array of precisely positioned contact elements — cantilever needles, vertical pins, or MEMS springs — that touch down on the die pads to carry test signals. Probe cards are custom-built per device pad layout.
An instrument that measures surface topography — step heights, roughness, film thickness at an etched step — either by dragging a fine stylus across the surface or by optical interferometry. Profilometers provide quick, direct thickness checks that complement optical film metrology.
An advanced packaging approach that processes packages on a large rectangular panel rather than a circular wafer or as separate package substrates. Panel-level packaging (PLP) includes fan-out panel-level packaging (FOPLP), in which singulated known-good die may be placed on a temporary carrier and reconstituted in molding compound, while other flows form the redistribution layer (RDL) before molding. A typical flow can include die placement or reconstitution, molding and carrier release, RDL formation and metal plating, thinning, inspection, and singulation. PLP is used for compact high-I/O packages and heterogeneous integration, including packages that combine multiple die or passive components. Compared with wafer-level packaging (WLP), its rectangular format can improve area utilization and potentially throughput for suitable package sizes; compared with conventional die/package assembly, fan-out routing can extend beyond the die footprint before packages are separated. Those advantages are process- and design-dependent: large panels require control of warpage, thermal stress, dimensional stability, die-shift and alignment, layer uniformity, handling, and yield, so PLP is not universally preferable to wafer-based or conventional assembly.
The master pattern plate — usually chrome on quartz — imaged by a projection exposure tool. In steppers and scanners the reticle pattern (often 4x or 5x the final size) is optically reduced onto each exposure field of the wafer. Also called a photomask, although "reticle" usually implies one exposure field rather than a full wafer image.
A dry-etch technique that combines chemically reactive plasma species with directional ion bombardment. The wafer sits on a powered electrode that develops a negative self-bias, accelerating ions toward the surface so etching proceeds vertically much faster than sideways — the anisotropy needed to transfer fine mask patterns.
Single-wafer heating — typically by banks of high-intensity lamps — that ramps the wafer to process temperature in seconds, holds briefly, and cools quickly. RTP is used for implant activation anneals, silicide formation, and thin oxidations where the long thermal budget of a batch furnace would diffuse dopants too far.
A projection lithography exposure tool that images the reticle pattern onto one exposure field of the wafer at a time, then steps the wafer stage to the next field and repeats. Steppers replaced full-wafer contact and proximity aligners because reduction projection optics allow finer resolution and better overlay.
A physical vapor deposition method in which energetic ions — usually argon from a plasma or magnetron discharge — bombard a solid target, ejecting atoms that condense on the wafer as a thin film. Sputtering is the dominant way metals and metal compounds such as aluminum, titanium, and TiN are deposited in device fabrication.
Applying a uniform thin liquid film — most importantly photoresist — by dispensing it onto a wafer spinning at high speed, where centrifugal force spreads and thins the fluid to a thickness set by spin speed and viscosity. Resist coat/develop "tracks" automate spin coating, baking, and developing inline with the exposure tool.
The consumable slab of source material eroded during sputter deposition. Target purity directly sets film purity, and targets are engineered — bonding, grain structure, shape — for uniform erosion; they are replaced on a preventive-maintenance schedule as they wear.
The narrow streets between adjacent die on a wafer, reserved for dicing. Scribe lines also carry process-control test structures and alignment marks that are sacrificed when the wafer is cut apart.
The SEMI communication standards (SECS-II message protocol and the GEM equipment model) through which factory host software controls and monitors production equipment — collecting events and sensor data, managing recipes, and driving fully automated lot processing.
A microscope that images the surface by scanning a focused electron beam and detecting emitted secondary electrons, resolving features far below the optical diffraction limit. Fab-dedicated CD-SEMs measure printed line widths in-line, and defect-review SEMs classify particles found by inspection tools.
The rate at which a tool processes wafers, normally quoted in wafers per hour (WPH) under stated conditions. Throughput, uptime, and yield together determine a tool's effective capacity, and equipment productivity is commonly tracked with the SEMI E10/OEE framework.
Growth of silicon dioxide by exposing silicon wafers to oxygen (dry oxidation) or steam (wet oxidation) at high temperature, consuming silicon from the surface as the oxide grows. Thermally grown oxide is the highest-quality SiO2 available and historically formed the gate dielectric and field isolation of MOS devices.
Forming the electrical connections between die bond pads and package leads with fine gold, copper, or aluminum wire. Thermosonic ball bonding and ultrasonic wedge bonding are the two main techniques; wire bonding remains the most widely used chip-interconnect method in packaging.
The thin, polished disc of single-crystal semiconductor — overwhelmingly silicon — on which integrated circuits are fabricated. Wafers are sliced from a grown crystal ingot and have standardized diameters; each generation of larger wafers (100, 150, 200, 300 mm) lowered the cost per die by carrying more chips per wafer.
Removal of particles, organic residues, and metallic contamination from wafer surfaces between process steps, classically with the RCA sequence of hydrogen-peroxide-based chemistries. Cleaning is the most frequently repeated operation in a fab, performed in wet benches or single-wafer spin processors.
Electrical testing of each die while still on the wafer. A wafer prober aligns the wafer so a probe card's needles or spring contacts land on the die's bond pads, and the connected tester runs the test program; failing die are logged in a wafer map so they are skipped at assembly.
Automated optical or e-beam scanning of wafers to find and map defects — particles, pattern faults, scratches — well before they become failing die. Inspection results feed defect-review and yield-analysis loops; patterned-wafer inspection compares each die image to its neighbors to isolate anomalies.
Separation of the finished wafer into individual die, conventionally with a high-speed diamond-blade dicing saw cutting along the scribe streets, and increasingly by laser scribing or plasma dicing for thin or delicate wafers. The wafer is mounted on adhesive tape in a film frame so the singulated die stay in place.
Material removal using liquid chemical baths, such as buffered HF for silicon dioxide or hot phosphoric acid for silicon nitride. Wet etches are typically isotropic (etching equally in all directions) but offer excellent selectivity between materials, so they remain common for film strips, cleans, and sacrificial-layer release.