Electroglas
EG 4090 u+
What it is
What can it run?
Process applications and technology nodes documented for this tool.
- Test & Probe
What do the numbers mean?
Power & electrical4
Control & software1
- Software EG Commander 9.5 on Windows 2K[2]
Configuration & options5
Vintage & configurations
Documented models & variants
| Designation | Generation | Vintage | Changes | Source |
|---|---|---|---|---|
| EG 4090 u | — | — | — | Equipment inventory listing[4] |
What replaced it?
Alternatives
Tools documented as functional equivalents — same process step and wafer size, from a different manufacturer. Each equivalence cites its source.
- Accretech UF 300 A Automatic Wafer— Same function class: Test & Probe, UnknownCompare in depthsource[5]
- Accretech UF 3000 Automatic Wafer— Same function class: Test & Probe, UnknownCompare in depthsource[5]
What does it need to run?
Site utility requirements, footprint, and infrastructure needed to install and operate this tool. Sourced from public records.
Where are the manuals?
Generated from public-source data on file. Enter your email to access — nothing is published; details are routed privately.
Not publicly documented
Field notes
No research found yet — worked with this tool? Share what you know.
Frequently asked questions
What is a test and probe system used for?General reference — not yet source-verified
It is used to make temporary electrical contact with wafer-level devices so their electrical properties can be measured before the wafer is diced.
What kind of work does this class perform in semiconductor manufacturing?General reference — not yet source-verified
It supports wafer-level inspection, electrical characterization, and screening of dies or test structures for process control and yield monitoring.
How does a machine in this class make contact with the wafer?General reference — not yet source-verified
It uses a precision stage and probe assembly to align the wafer and place fine probes onto conductive pads or test structures.
Where does this class fit in the process flow?General reference — not yet source-verified
It is used after fabrication and before singulation, when devices are still organized on the wafer.
Why is wafer-level test important?General reference — not yet source-verified
It helps identify electrical behavior, process variation, and defective sites before later assembly steps.
Not publicly documented
The following facts about the EG 4090 u+ are absent from this record as of this revision. First-hand knowledge or a citation closes a gap; every submission is reviewed before publication.
No publicly documented production dates or lifecycle milestones (introduction, end of production, EOL) for the EG 4090 u+ are on record.
Answerable by: OEM historical records or a trade-press announcement
The control-system platform and OS era of the EG 4090 u+ are not on record.
Answerable by: an engineer who operated it or OEM installation records
No publicly documented failure modes or field errata for the EG 4090 u+ are on record.
Answerable by: a field service engineer, process engineer, or maintenance technician
The process node or technology generation of the EG 4090 u+ is not on record.
Answerable by: an OEM datasheet or a fab qualification report
No publicly documented compatible parts, consumables, or accessories for the EG 4090 u+ are on record.
Answerable by: an OEM parts catalog or a service engineer
No research found yet — worked with this tool? Share what you know.
Sources & citations
Sources (7)Every fact above is drawn from these public sources
- [1]Inventory photo
- [2]Inventory photo
- [3]Inventory photo
- [4]Equipment inventory listing
- [5]Equipment inventory listing
- [6]Equipment inventory listing
- [7]Equipment inventory listing
Last updated Jul 29, 2026.
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