Fab planning
Start with a planning guide for your process, then use the interactive planner to shape a cited equipment list around your wafer size, scale, and sourcing constraints. Guides link only to public catalog categories and published equipment entries.
Start the interactive fab planner →Integrated photonics, waveguides, lasers on chip
Sensors, actuators, microstructures
Co-packaged optics, optical I/O
GaN, SiC, GaAs, InP
2.5D/3D, fan-out, chiplets
Image sensors, detectors, arrays
MOSFETs, IGBTs, modules
Qubits, JJs, cryo-electronics
Multi-user research fabs
AI accelerator BEOL, HBM stacks, CoWoS interposers
Labs, QA, characterization
Process development, packaging evaluation, and failure analysis
These planning pages map equipment categories to the manufacturing steps behind AI accelerators, HBM, co-packaged optics, and power semiconductors. They are planning references, not facility-product recommendations.
Silicon carbide (SiC) wafer fabrication requires specialized equipment for epitaxy, high-temperature ion implantation, and hard-material etch. SiC's extreme hardness and chemical inertness demand tools designed beyond standard silicon limits. This page covers the key process steps, required equipment categories, and top tool picks for SiC power device manufacturing.
Gallium nitride (GaN) epitaxy uses MOCVD reactors, HVPE systems, and specialized MBE tools to grow device-quality III-nitride layers on silicon, sapphire, or SiC substrates. GaN enables high-voltage/high-frequency power devices and RF transistors. This page covers the required equipment categories and top tool picks for GaN-on-Si, GaN-on-SiC, and GaN-on-sapphire processes.
Chip-on-Wafer-on-Substrate (CoWoS) is TSMC's 2.5D integration platform that stacks HBM alongside logic dies on a silicon interposer. Producing CoWoS packages requires front-end-like lithography, bonding, and inspection tools. This page covers the lithography, bonding, and metrology equipment required for CoWoS and similar advanced packaging processes.
High Bandwidth Memory (HBM) packaging stacks DRAM dies with through-silicon vias (TSVs) and copper pillars. TSV formation, wafer thinning, and precision bonding require a dedicated equipment set distinct from standard DRAM production. This page covers the TSV drilling, wafer thinning, bonder, and inspection tools required for HBM2, HBM3, and HBM4 manufacturing.
Compound semiconductor fabrication for GaAs, InP, GaN, and SiC devices requires MOCVD/MBE epitaxy, specialized etch, and compound-safe wet processing. III-V and IV-IV materials are reactive and require chemistries and chamber materials that differ from standard silicon fabs. This page covers the equipment categories and top tools for compound semiconductor manufacturing.
A planning pillar connecting facility constraints to the semiconductor supply chain without presenting unverified facility inventory.